This invention relates to logic circuits and more particularly to transistor switching circuits having low speed/power product.
In the development of data processing equipment, extensive effort is being directed to integrated circuits having improved speed capabilities and speed/power factor.
In particular, as the logic circuit density and chip size increases for VLSI technologies, the requirement exists for logic circuits having the capability to drive high capacitance on chip loads at acceptable speed/power factors.
Prior art bipolar logic circuits such as DTL, TTL and ECL must operate at high power levels if low delay is required at high load capacitance. This relationship is due to the fact that active drive is available for only one output transition, while the other transition depends on the time constant of the output load resistance and capacitive load.
A technique to achieve good capacitive drive is to incorporate a push-pull circuit in the output. The push-pull circuit is well known to the art and is used extensively in off chip drivers and also in complementary NPN/PNP bipolar circuits. The logic circuit in accordance with the invention exhibits push-pull output characteristic by employing saturated feedback technique. This approach allows for emitter follower like up level drive and transient low impedance down level drive. The saturated feedback technique improves capacitive drive capability, reduces both load and circuit delay and reduces circuit power dissipation.
As with other circuits containing push-pull outputs, the logical dot function is avoided to eliminate a circuit contention problem.
There is a very sizeable number of logic circuits known to the art. It is to be appreciated with reference to the subject invention, that, the following art is not submitted to be the only prior art, the best prior art, or the most pertinent prior art.